@article {735,
	title = {On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators},
	journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume = {73},
	year = {2026},
	month = {March},
	pages = {1777-1786},
	abstract = {Despite extensive research, the upconversion of 1/f noise into phase noise in harmonic oscillators is still an open topic of investigation. A few upconversion mechanisms are not fully understood yet. In particular, in class-B CMOS oscillators, the reason why a large tail capacitance combined with transistors entering the triode region for a portion of the oscillation cycle dramatically amplifies the 1/f noise upconversion has not been clearly pinpointed. This work introduces a simple yet powerful model to fully capture the 1/f noise upconversion mechanism. It shows that when the transistors enter the triode region, charge sharing between the tail capacitance and the tank capacitance injects a noise charge into the tank, generating phase noise perturbations quantified by the impulse sensitivity function. The analytical description results in closed-form equations that predict the $1/f^3$ phase noise sideband accurately, without relying on complex harmonic analysis or specific device nonlinearities. The excellent agreement with simulations performed both using idealized and real 55nm CMOS transistor models confirms the validity and robustness of the proposed framework, offering new insights and practical design guidelines for low phase noise CMOS oscillators.},
	keywords = {1/f noise, Capacitance, Circuits, CMOS oscillators, Equivalent circuits, Harmonic analysis, Impulse sensitivity function, Integrated circuit modeling, Perturbation methods, phase noise, Semiconductor device modeling, transistors},
	issn = {1558-0806},
	doi = {10.1109/TCSI.2025.3602924},
	author = {Bevilacqua, A. and Mazzanti, Andrea}
}
@article {665,
	title = {Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs},
	journal = {IEEE Journal of Solid-State Circuits},
	volume = {59},
	year = {2024},
	pages = {294-306},
	keywords = {CMOS, coupled phase-locked loop (CPLL), Couplings, Harmonic analysis, Mixers, phase locked loops, phase noise, quadrature voltage-controlled oscillator (QVCO), radio frequency integrated circuits (RFIC), Steady-state, voltage-controlled oscillators},
	doi = {10.1109/JSSC.2023.3280360},
	author = {Iesurum, Agata and Manente, Davide and Padovan, Fabio and Bassi, Matteo and Bevilacqua, A.}
}
@article {685,
	title = {On the Benefits of the Common-Mode Resonance on the 1/f {\texttwosuperior} Phase Noise Sideband},
	journal = {IEEE Transactions on Circuits and Systems II: Express Briefs},
	volume = {71},
	year = {2024},
	pages = {3715-3719},
	keywords = {Amplitude modulation, Class-B, Class-F$_{2}$, class-J, Common-mode resonance, Harmonic analysis, Harmonic Oscillators, phase noise, Power harmonic filters, Thermal noise, Topology, transistors, VCOs},
	doi = {10.1109/TCSII.2024.3376717},
	author = {Bellemo, Luca and Bevilacqua, A.}
}
@article {511,
	title = {A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS},
	journal = {IEEE Solid-State Circuits Letters},
	volume = {2},
	year = {2019},
	month = {Sep.},
	pages = {107-110},
	keywords = {5G communication systems, 5G mobile communication, Bandwidth, BiCMOS technologies, bulk CMOS technology, carrier signal generation, CMOS, CMOS analogue integrated circuits, communication systems, edge-combining concept, field effect MMIC, fifth generation (5G), frequency 39 GHz, Frequency conversion, Frequency measurement, frequency multiplier, frequency multipliers, frequency tripler, Harmonic analysis, harmonic rejection, harmonics suppression, high harmonic rejection ratio, injection locked oscillators, low phase noise, low spur level, mm-waves, MMIC frequency convertors, multipoint injection-locked ring oscillator, phase noise, power 25.0 mW, radar, Ring oscillators, robust rejection ratio, single-stage polyphase filter, size 28 nm, tripler, V, voltage 0.9 V},
	issn = {2573-9603},
	doi = {10.1109/LSSC.2019.2930198},
	author = {M. Bassi and G. Boi and F. Padovan and J. Fritzin and S. Di Martino and D. Knauder and Bevilacqua, A.}
}
@article {465,
	title = {Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique},
	journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume = {65},
	year = {2018},
	pages = {3780 - 3789},
	keywords = {AM-PM distortion., Capacitance, class-J, Distortion, Harmonic analysis, Impedance, ladder filter, power amplifier, Power harmonic filters, SiGe, Silicon germanium, transistors, X-Band},
	issn = {1549-8328},
	doi = {10.1109/TCSI.2018.2858573},
	author = {P. Scaramuzza and C. Rubino and M. Caruso and M. Tiebout and Bevilacqua, A. and A. Neviani}
}
@article {7999240,
	title = {On the Remarkable Performance of the Series-Resonance CMOS Oscillator},
	journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume = {65},
	number = {2},
	year = {2018},
	month = {Feb},
	pages = {531-542},
	keywords = {Harmonic analysis, Impedance, impulse sensitivity function (ISF), Inverters, MOS devices, oscillators, phase noise, Topology},
	issn = {1549-8328},
	doi = {10.1109/TCSI.2017.2727283},
	author = {F. Pepe and Bevilacqua, A. and Andreani, P.}
}
@article {6939739,
	title = {A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications},
	journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume = {62},
	number = {2},
	year = {2015},
	month = {Feb},
	pages = {413-422},
	keywords = {CMOS, Frequency conversion, frequency divider, frequency division, Harmonic analysis, harmonic rejection, phase locked loops, Radar imaging, receivers, stepped frequency continuous wave (SFCW), transmitters, UWB transmitter},
	issn = {1549-8328},
	doi = {10.1109/TCSI.2014.2362332},
	author = {Caruso, M. and Bassi, M. and Bevilacqua, A. and Neviani, A.}
}
