@article {511,
	title = {A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS},
	journal = {IEEE Solid-State Circuits Letters},
	volume = {2},
	year = {2019},
	month = {Sep.},
	pages = {107-110},
	keywords = {5G communication systems, 5G mobile communication, Bandwidth, BiCMOS technologies, bulk CMOS technology, carrier signal generation, CMOS, CMOS analogue integrated circuits, communication systems, edge-combining concept, field effect MMIC, fifth generation (5G), frequency 39 GHz, Frequency conversion, Frequency measurement, frequency multiplier, frequency multipliers, frequency tripler, Harmonic analysis, harmonic rejection, harmonics suppression, high harmonic rejection ratio, injection locked oscillators, low phase noise, low spur level, mm-waves, MMIC frequency convertors, multipoint injection-locked ring oscillator, phase noise, power 25.0 mW, radar, Ring oscillators, robust rejection ratio, single-stage polyphase filter, size 28 nm, tripler, V, voltage 0.9 V},
	issn = {2573-9603},
	doi = {10.1109/LSSC.2019.2930198},
	author = {M. Bassi and G. Boi and F. Padovan and J. Fritzin and S. Di Martino and D. Knauder and Bevilacqua, A.}
}
