@conference {7527337,
	title = {A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior},
	booktitle = {2016 IEEE International Symposium on Circuits and Systems (ISCAS)},
	year = {2016},
	month = {May},
	pages = {702-705},
	keywords = {algorithm ciclicity, Algorithm design and analysis, bidirectional data-weighted averaging algorithm, CMOS digital integrated circuits, CMOS technology, Complexity theory, DAC, device mismatch, digital to analog converters, digital-analogue conversion, Hardware, hardware complexity, integrated circuit modelling, Mathematical model, Modulation, Multiplexing, sigma-delta modulation, sigma-delta modulators, size 65 nm, spurs immunity, Standards},
	doi = {10.1109/ISCAS.2016.7527337},
	author = {A. Celin and Gerosa, A.}
}
@conference {7168918,
	title = {Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs},
	booktitle = {2015 IEEE International Symposium on Circuits and Systems (ISCAS)},
	year = {2015},
	month = {May},
	pages = {1454-1457},
	keywords = {Algorithm design and analysis, analog-to-digital converter, Clocks, CMOS digital integrated circuits, CMOS integrated circuits, CMOS technologies, CMOS technology, data weighted averaging, DEM algorithms, dynamic element matching algorithms, hardware complexity, Heuristic algorithms, internal DAC, logic design, mismatch cancellation, Modulation, multibit sigma-delta ADC, multibit ΣΔ ADC, Noise, optimal DWA design, sigma-delta modulation, sigma-delta modulator, size 65 nm, Timing, ΣΔ modulator},
	issn = {0271-4302},
	doi = {10.1109/ISCAS.2015.7168918},
	author = {A. Celin and Gerosa, A.}
}
