L.  Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., ?Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters?, IEEE Transactions on Microwave Theory and Techniques, vol. 72, pp. 2840-2851, 2024.

L.  Tomasin, Iesurum, A., Gobbo, A., Neviani, A., and Bevilacqua, A., ?A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 4718-4722, 2024.

F.  Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., ?A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner?, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

L.  Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., ?A Reactive Passive Mixer for 16-QAM Cartesian IoT Transmitters in 22 nm FD-SOI CMOS?, in 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2023.

L.  Tomasin and Bevilacqua, A., ?A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem?, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.

L.  Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., ?A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise?, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., ?A 68.6fs_rms-Total-integrated-Jitter and 1.5?s-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching?, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

F.  Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., ?A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler?, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

S. M.  Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., ?A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 ? s-Locking-Time?, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.

L.  Tomasin, Boi, G., Padovan, F., and Bevilacqua, A., ?A 10.7?14.1 GHz Reconfigurable Octacore DCO with ?126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS?, in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.

S.  Veni, Andreani, P., Caruso, M., Tiebout, M., and Bevilacqua, A., ?Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO?, IEEE Journal of Solid-State Circuits, vol. 55, pp. 2345-2355, 2020.

S.  Veni, Caruso, M., Tiebout, M., and Bevilacqua, A., ?A 17 GHz All-npn Push-Pull Class-C VCO?, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

F.  Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., ?A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications?, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.

P.  Scaramuzza, Rubino, C., Caruso, M., Tiebout, M., Bevilacqua, A., and Neviani, A., ?Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3780 - 3789, 2018.

S.  Marconi, Barbero, M. B., Fougeron, D., Godiot, S., Menouni, M., Pangaud, P., Rozanov, A., Breugnon, P., Bomben, M., Calderini, G., Crescioli, F., Le Dortz, O., Marchiori, G., Dzahini, D., Rarbi, F. E., Gaglione, R., Krüger, H., Daas, M., Dieter, Y., Hemperek, T., Hügging, F., Moustakas, K., Pohl, D., Rymaszewski, P., Standke, M., Vogt, M., Wang, T., Wermes, N., Karagounis, M., Stiller, A., Marzocca, C., Marzocca, G., De Robertis, G., Loddo, F., Licciulli, F., Andreazza, A., Liberali, V., Stabile, A., Frontini, L., Bagatin, M., Bisello, D., Gerardin, S., Mattiazzo, S., Paccagnella, A., Vogrig, D., Bonaldo, S., Bacchetta, N., Gaioni, L., De Canio, F., Manghisoni, M., Re, V., Riceputi, E., Traversi, G., Ratti, L., Vacchi, C., Androsov, K., Beccherle, R., Magazzu, G., Minuti, M., Morsani, F., Palla, F., Poulios, S., Bilei, G. M., Menichelli, M., Placidi, P., Dellacasa, G., Demaria, N., Mazza, G., Monteil, E., Pacher, L., Paternò, A., Rivetti, A., Rolo, M. D. Da Roch, Gajanana, D., Gromov, V., van Eijk, B., Kluit, R., Vitkovskiy, A., Benka, T., Havranek, M., Janoska, Z., Marcisovsky, M., Neue, G., Tomasek, L., Kafka, V., Vrba, V., Lopez-Morillo, E., Palomo, F. R., Muñoz, F., Vila, I., Jiménez, E. M. S., Abbaneo, D., Christiansen, J., Orfanelli, S., Casas, L. M. Jara, Conti, E., Bell, S., Prydderch, M. L., Thomas, S., Christian, D. C., Deptuch, G., Fahim, F., Hoff, J., Lipton, R., Liu, T., Zimmerman, T., Miryala, S., Garcia-Sciveres, M., Gnani, D., Krieger, A., Papadopoulou, K., Heim, T., Carney, R., Nachman, B., Renteira, C., Wallangen, V., Hoeferkamp, M., and Seidel, S., ?Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC?, in 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), 2018.

F.  Padovan, Quadrelli, F., Bassi, M., Tiebout, M., and Bevilacqua, A., ?A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations?, in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018.

A.  Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., ?A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE?, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.

F.  Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset?, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.

P.  Scaramuzza, Rubino, C., Tiebout, M., Caruso, M., Ortner, M., Neviani, A., and Bevilacqua, A., ?Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems?, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 187-190.

F.  Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation?, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.

F.  Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers?, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.

F.  Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation?, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.

F.  Padovan, Tiebout, M., Mertens, K. L. R., Bevilacqua, A., and Neviani, A., ?Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 607-615, 2015.

F.  Padovan, Tiebout, M., Dielacher, F., Bevilacqua, A., and Neviani, A., ?SiGe BiCMOS VCO with 27% tuning range for 5G communications?, in 2015 Asia-Pacific Microwave Conference (APMC), 2015, vol. 1, pp. 1-3.

F.  Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., ?A K-band SiGe bipolar VCO with transformer-coupled varactor for backhaul links?, in 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF),, 2013, pp. 108-110.

F.  Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., ?A SiGe bipolar VCO for backhaul E-band communication systems?, in Proceedings of the 2012 ESSCIRC, 2012, pp. 402 -405.

M.  Camponeschi, Bevilacqua, A., Tiebout, M., and Neviani, A., ?A X-Band I/Q Upconverter in 65 nm CMOS for High Resolution FMCW Radars?, IEEE Microwave and Wireless Components Letters, vol. 22, pp. 141 -143, 2012.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., ?A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS?, IEEE Journal of Solid-State Circuits, vol. 45, pp. 1295 -1304, 2010.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., ?An Integrated Divide-by-Two Direct Injection-Locking Frequency Divider for Bands S Through Ku?, IEEE Transactions on Microwave Theory and Techniques, vol. 58, pp. 1686 -1695, 2010.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., ?A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS?, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.

A.  Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems?, IEEE Journal of Solid-State Circuits, vol. 44, pp. 331 -343, 2009.

A.  Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS?, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.

A.  Bevilacqua, Camponeschi, M., Tiebout, M., Gerosa, A., and Neviani, A., ?Design of broadband inductorless LNAs in ultra-scaled CMOS technologies?, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008. , 2008, pp. 1300 -1303.

S. D.  Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, in Digest of Technical Papers of 2008 IEEE International Solid-State Circuits Conference, 2008, pp. 124 -601.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2844 -2852, 2008.

A.  Bevilacqua, Vallese, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers?, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.

A.  Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS?, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.