D.  Frassetto, Cabizza, S., Zilio, N. ', Karim, A., Garbossa, C., Agostinelli, M., Spiazzi, G., Bevilacqua, A., and Neviani, A., ?A Highly Integrated Dual-Path Step-Down Hybrid DC?DC Converter With Self-Balanced Flying Capacitor and Reduced Inductor Current?, IEEE Open Journal of Power Electronics, vol. 7, pp. 167-179, 2026.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS?, IEEE Solid-State Circuits Letters, vol. 8, pp. 217 - 220, 2025.

D.  Frassetto, Cabizza, S., Karim, A., Spiazzi, G., Bevilacqua, A., and Neviani, A., ?Accurate Analysis of Switching Transients in the High-Frequency, Integrated Dual-Path Step-Down DC-DC Converter?, in 2025 IEEE Nordic Circuits and Systems Conference (NorCAS), 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications?, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

D.  Frassetto, Cabizza, S., Agostinelli, M., Garbossa, C., Spiazzi, G., Bevilacqua, A., and Neviani, A., ?Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters?, in 2025 International Conference on IC Design and Technology (ICICDT), 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers?, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-9, 2025.

L.  Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., ?A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1?s?, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers?, in 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024.

L.  Bellemo, Spiazzi, G., and Bevilacqua, A., ?On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting?, in 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024.

F.  Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., ?A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner?, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., ?A 68.6fs_rms-Total-integrated-Jitter and 1.5?s-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching?, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

F.  Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., ?A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler?, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

A.  Bettini, Cosnier, T., Magnani, A., Syshchyk, O., Borga, M., Decoutere, S., and Neviani, A., ?Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology?, in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022.

F.  Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications?, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

S. M.  Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., ?A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 ? s-Locking-Time?, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.

C.  Shi, Song, M., Gao, Z., Bevilacqua, A., Dolmans, G., and Liu, Y. - H., ?Galvanic-Coupled Trans-Dural Data Transfer for High-Bandwidth Intracortical Neural Sensing?, IEEE Transactions on Microwave Theory and Techniques, vol. 70, pp. 4579-4589, 2022.

F.  Chiocchetta, De Santi, C., Rampazzo, F., Mukherjee, K., Grünenpütt, J., Sommer, D., Blanck, H., Lambert, B., Gerosa, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., ?GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse?, in 2022 IEEE International Reliability Physics Symposium (IRPS), 2022.

S.  Veni, Caruso, M., Seebacher, D., Neviani, A., and Bevilacqua, A., ?A Fully Integrated 28 GHz Class-J Doherty Power Amplifier in 130 nm BiCMOS?, in SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, 2021.

G.  Marin, Kim, J., Seo, J. - M., and Neviani, A., ?A 13.56 MHz Reconfigurable Step-Up Switched Capacitor Converter for Wireless Power Transfer System in Implantable Medical Devices?, in 2020 IEEE Wireless Power Transfer Conference (WPTC), 2020.

D.  Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., ?A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS?, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.

S.  Marconi, Spiazzi, G., Bevilacqua, A., and Galvano, M., ?A Novel Integrated Step-Up Hybrid Converter With Wide Conversion Ratio?, IEEE Transactions on Power Electronics, vol. 35, pp. 2764-2775, 2020.

G.  Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., ?Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters?, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.

G.  Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., ?A Reconfigurable Switched Capacitor DC?DC Converter With 1.9?6.3-V Input Voltage Range and 85% Peak Efficiency in 28-nm CMOS?, IEEE Solid-State Circuits Letters, vol. 3, pp. 106-109, 2020.

A.  Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., ?A 130-nm CMOS Dual Input-Polarity DC?DC Converter for Low-Power Applications?, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.

M.  Ruzzarin, Meneghini, M., de Santi, C., Neviani, A., Yu, F., Strempel, K., Fatahilah, M. Fahlesa, Witzigmann, B., Wasisto, H. Suryo, Waag, A., Meneghesso, G., and Zanoni, E., ?Demonstration of UV-Induced Threshold Voltage Instabilities in Vertical GaN Nanowire Array-Based Transistors?, IEEE Transactions on Electron Devices, vol. 66, pp. 2119-2124, 2019.

G.  Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., ?Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters?, in 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019.

A.  Gerosa, Bevilacqua, A., and Spiazzi, G., ?A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology?, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019.

G.  Spiazzi, Biadene, D., Marconi, S., and Bevilacqua, A., ?Non-isolated High Step-up DC-DC Converter with Minimum Switch Voltage Stress?, IEEE Transactions on Power Electronics, vol. 34, no. 2, pp. 1470-1480, 2019.

P.  Scaramuzza, Rubino, C., Caruso, M., Tiebout, M., Bevilacqua, A., and Neviani, A., ?Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3780 - 3789, 2018.

S.  Marconi, Barbero, M. B., Fougeron, D., Godiot, S., Menouni, M., Pangaud, P., Rozanov, A., Breugnon, P., Bomben, M., Calderini, G., Crescioli, F., Le Dortz, O., Marchiori, G., Dzahini, D., Rarbi, F. E., Gaglione, R., Krüger, H., Daas, M., Dieter, Y., Hemperek, T., Hügging, F., Moustakas, K., Pohl, D., Rymaszewski, P., Standke, M., Vogt, M., Wang, T., Wermes, N., Karagounis, M., Stiller, A., Marzocca, C., Marzocca, G., De Robertis, G., Loddo, F., Licciulli, F., Andreazza, A., Liberali, V., Stabile, A., Frontini, L., Bagatin, M., Bisello, D., Gerardin, S., Mattiazzo, S., Paccagnella, A., Vogrig, D., Bonaldo, S., Bacchetta, N., Gaioni, L., De Canio, F., Manghisoni, M., Re, V., Riceputi, E., Traversi, G., Ratti, L., Vacchi, C., Androsov, K., Beccherle, R., Magazzu, G., Minuti, M., Morsani, F., Palla, F., Poulios, S., Bilei, G. M., Menichelli, M., Placidi, P., Dellacasa, G., Demaria, N., Mazza, G., Monteil, E., Pacher, L., Paternò, A., Rivetti, A., Rolo, M. D. Da Roch, Gajanana, D., Gromov, V., van Eijk, B., Kluit, R., Vitkovskiy, A., Benka, T., Havranek, M., Janoska, Z., Marcisovsky, M., Neue, G., Tomasek, L., Kafka, V., Vrba, V., Lopez-Morillo, E., Palomo, F. R., Muñoz, F., Vila, I., Jiménez, E. M. S., Abbaneo, D., Christiansen, J., Orfanelli, S., Casas, L. M. Jara, Conti, E., Bell, S., Prydderch, M. L., Thomas, S., Christian, D. C., Deptuch, G., Fahim, F., Hoff, J., Lipton, R., Liu, T., Zimmerman, T., Miryala, S., Garcia-Sciveres, M., Gnani, D., Krieger, A., Papadopoulou, K., Heim, T., Carney, R., Nachman, B., Renteira, C., Wallangen, V., Hoeferkamp, M., and Seidel, S., ?Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC?, in 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), 2018.

P.  Scaramuzza, Rubino, C., Tiebout, M., Caruso, M., Ortner, M., Neviani, A., and Bevilacqua, A., ?Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems?, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 187-190.

G.  Spiazzi, Biadene, D., Marconi, S., and Bevilacqua, A., ?Non-isolated high step-up DC-DC converter with minimum switch voltage stress?, in 2017 IEEE Southern Power Electronics Conference (SPEC), 2017.

G.  Spiazzi, Marconi, S., and Bevilacqua, A., ?Step-Up DC-DC converters combining basic topologies with charge pump?, in 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), 2016, pp. 1-6.

M.  Bassi, Zhao, J., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., ?A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP?, IEEE Journal of Solid-State Circuits, vol. 50, pp. 1618-1628, 2015.

J.  Zhao, Bassi, M., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., ?A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP?, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 179-182.

S.  Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., ?A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13um CMOS?, IEEE Journal of Solid-State Circuits, vol. 46, pp. 1636 -1647, 2011.

S.  Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., ?A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request?, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.

A.  Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., ?A digitally programmable ring oscillator in the UWB range?, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),, 2010, pp. 1101 -1104.

S.  Soldà, Caruso, M., Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., ?Low-power UWB transmitter using a combined mixer and power amplifier?, in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 333 -336.

A.  Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems?, IEEE Journal of Solid-State Circuits, vol. 44, pp. 331 -343, 2009.

A.  Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., ?An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, pp. 1030 -1040, 2009.

A.  Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS?, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.

S.  Soldà, Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., ?Analog decoding of trellis coded modulation for multi-level flash memories?, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., 2008, pp. 744 -747.

S. D.  Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, in Digest of Technical Papers of 2008 IEEE International Solid-State Circuits Conference, 2008, pp. 124 -601.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2844 -2852, 2008.

A.  Bevilacqua, Vallese, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers?, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.

A.  Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., ?A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver?, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.

A.  Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., ?An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS?, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.

A.  Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., ?Quadrature VCOs Based on Coupled PLLs?, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 2140 -2143.

A.  Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., ?Transformer-Based Dual-Mode Voltage-Controlled Oscillators?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, pp. 293 -297, 2007.

A.  Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., ?A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO?, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.

A.  Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., ?A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers?, IEEE Microwave and Wireless Components Letters, vol. 16, pp. 134 -136, 2006.

A.  Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., SOLDA, S., Neviani, A., and Gerosa, A., ?Iterative Analog Decoder for a SCCC?, in Analog Decoding Workshop, 2006.

A.  Bevilacqua and Svelto, F., ?Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, pp. 117 - 121, 2005.

A.  Bevilacqua and Svelto, F., ?Non-linear spectral analysis of direct conversion wireless receivers?, in IEEE 2002 Radio and Wireless Conference, 2002, pp. 39 - 42.

G.  MENEGHESSO, Zanoni, E., Gerosa, A., PAVAN, P., STADLER, W., ESMARK, K., and GUGGENMOS, G., ?Test structures and testing methods for electrostatic discharge: results of PROPHECY project?, MICROELECTRONICS RELIABILITY, vol. 39, pp. 635?646, 1999.