@conference {688,
	title = {A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs},
	booktitle = {2024 IEEE European Solid-State Electronics Research Conference (ESSERC)},
	year = {2024},
	keywords = {CMOS, Digital Phase-locked loops (DPLLs), digital pre-distortion, digitally-controlled oscillator (DCO), fast locking, Frequency modulation, frequency synthesizers, Jitter, mm-Wave, Phase modulation, Power demand, Prototypes, Spread spectrum communication, Standards, Time-frequency analysis, Transient analysis, Wireless communication},
	doi = {10.1109/ESSERC62670.2024.10719534},
	author = {Grimaldi, Luigi and Iesurum, Agata and Boi, Giovanni and Versolatto, Fabio and Steffan, Giovanni and Padovan, Fabio and Koltsov, Heorhii and Bevilacqua, A. and Cherniak, Dmytro}
}
@article {642,
	title = {A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner},
	journal = {IEEE Journal of Solid-State Circuits},
	volume = {58},
	year = {2023},
	pages = {634-646},
	doi = {10.1109/JSSC.2022.3228899},
	author = {Buccoleri, Francesco and Dartizio, Simone M. and Tesolin, Francesco and Avallone, Luca and Santiccioli, Alessio and Iesurum, Agata and Steffan, Giovanni and Cherniak, Dmytro and Bertulessi, Luca and Bevilacqua, A. and Samori, Carlo and Lacaita, Andrea L. and Levantino, Salvatore}
}
@conference {577,
	title = {A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching},
	booktitle = {2022 IEEE International Solid- State Circuits Conference (ISSCC)},
	year = {2022},
	doi = {10.1109/ISSCC42614.2022.9731683},
	author = {Dartizio, Simone Mattia and Buccoleri, Francesco and Tesolin, Francesco and Avallone, Luca and Santiccioli, Alessio and Iesurum, Agata and Steffan, Giovanni and Cherniak, Dmytro and Bertulessi, Luca and Bevilacqua, A. and Samori, Carlo and Lacaita, Andrea Leonardo and Levantino, Salvatore}
}
@conference {580,
	title = {A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler},
	booktitle = {2022 IEEE Custom Integrated Circuits Conference (CICC)},
	year = {2022},
	doi = {10.1109/CICC53496.2022.9772796},
	author = {Buccoleri, Francesco and Dartizio, Simone M. and Tesolin, Francesco and Avallone, Luca and Santiccioli, Alessio and Lesurum, Agata and Steffan, Giovanni and Bevilacqua, A. and Bertulessi, Luca and Cherniak, Dmytro and Samori, Carlo and Lacaita, Andrea L. and Levantino, Salvatore}
}
@article {623,
	title = {A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time},
	journal = {IEEE Journal of Solid-State Circuits},
	year = {2022},
	pages = {1-14},
	doi = {10.1109/JSSC.2022.3206955},
	author = {Dartizio, Simone M. and Buccoleri, Francesco and Tesolin, Francesco and Avallone, Luca and Santiccioli, Alessio and Iesurum, Agata and Steffan, Giovanni and Cherniak, Dmytro and Bertulessi, Luca and Bevilacqua, A. and Samori, Carlo and Lacaita, Andrea L. and Levantino, Salvatore}
}
