L.  Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., ?A 0.13-?m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication?, IEEE Journal of Solid-State Circuits, pp. 1-12, 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS?, IEEE Solid-State Circuits Letters, vol. 8, pp. 217 - 220, 2025.

D.  Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., ?A 5.1?10.5 GHz SiGe BiCMOS Power Amplifier for 6GNR with 29 dBm PSAT and 40.1% PAE?, in 2025 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2025.

D.  Pecile, Pollin, A., Dal Maistro, D., Gambarucci, A., De Astis, G., and Bevilacqua, A., ?A 5-7 GHz BiCMOS Front-End Module for WiFi 6e with 2.2 dB NF and 16 dBm PAVG at ?40 dB EVM?, in 2025 20th European Microwave Integrated Circuits Conference (EuMIC), 2025.

L.  Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., ?A 5.75mW Fully-Integrated Galvanic Isolator for Gate Drivers with Asynchronous 66.7/66.7 Mb/s Full-Duplex Communication?, in 2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2025.

D.  Pecile, Gambarucci, A., Kokorovic, S., and Bevilacqua, A., ?Analysis and Design of a SiGe BiCMOS PA for 6G FR3 Band With 29-dBm P SAT and 40.1% PAE?, IEEE Transactions on Microwave Theory and Techniques, pp. 1-12, 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications?, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers?, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-9, 2025.

L.  Navarin, Norling, K., Parenzan, M., Ruzzu, S., Neviani, A., and Bevilacqua, A., ?A Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication?, IEEE Solid-State Circuits Letters, vol. 8, pp. 289-292, 2025.

D.  Pecile, Gambarrucci, A., Kokorovic, S., and Bevilacqua, A., ?A Study of the Efficiency of Output-Matched Radiofrequency Power Amplifiers?, Analog Integrated Circuits and Signal Processing, vol. 125, no. 3, p. 42, 2025.

L.  Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., ?A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1?s?, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

A.  Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., ?Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs?, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., ?On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers?, in 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024.

D.  Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., ?On the Efficiency of Output-Matched Radiofrequency Power Amplifiers?, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

D.  Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, pp. 607-617, 2023.

L.  Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., ?A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise?, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.

A.  Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., ?A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS?, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

F.  Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications?, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

N.  Modolo, De Santi, C., Baratella, G., Bettini, A., Borga, M., Posthuma, N., Bakeroot, B., You, S., Decoutere, S., Bevilacqua, A., Neviani, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., ?Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices?, IEEE Transactions on Electron Devices, pp. 1-6, 2022.

L.  Tomasin, Boi, G., Padovan, F., and Bevilacqua, A., ?A 10.7?14.1 GHz Reconfigurable Octacore DCO with ?126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS?, in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.

A.  Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS?, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.

D.  Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A 22?31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS?, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021.

A.  Franceschin, Andreani, P., Padovan, F., Bassi, M., and Bevilacqua, A., ?A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects?, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1842-1853, 2020.

D.  Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., ?A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS?, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.

F.  Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., ?A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications?, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.

A.  Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., ?A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion?, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.

M.  Bassi, Boi, G., Padovan, F., Fritzin, J., Di Martino, S., Knauder, D., and Bevilacqua, A., ?A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS?, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.

A.  Passamani, Ponton, D., Wolter, A., Knoblinger, G., and Bevilacqua, A., ?A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner?, in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018.

S.  Marconi, Barbero, M. B., Fougeron, D., Godiot, S., Menouni, M., Pangaud, P., Rozanov, A., Breugnon, P., Bomben, M., Calderini, G., Crescioli, F., Le Dortz, O., Marchiori, G., Dzahini, D., Rarbi, F. E., Gaglione, R., Krüger, H., Daas, M., Dieter, Y., Hemperek, T., Hügging, F., Moustakas, K., Pohl, D., Rymaszewski, P., Standke, M., Vogt, M., Wang, T., Wermes, N., Karagounis, M., Stiller, A., Marzocca, C., Marzocca, G., De Robertis, G., Loddo, F., Licciulli, F., Andreazza, A., Liberali, V., Stabile, A., Frontini, L., Bagatin, M., Bisello, D., Gerardin, S., Mattiazzo, S., Paccagnella, A., Vogrig, D., Bonaldo, S., Bacchetta, N., Gaioni, L., De Canio, F., Manghisoni, M., Re, V., Riceputi, E., Traversi, G., Ratti, L., Vacchi, C., Androsov, K., Beccherle, R., Magazzu, G., Minuti, M., Morsani, F., Palla, F., Poulios, S., Bilei, G. M., Menichelli, M., Placidi, P., Dellacasa, G., Demaria, N., Mazza, G., Monteil, E., Pacher, L., Paternò, A., Rivetti, A., Rolo, M. D. Da Roch, Gajanana, D., Gromov, V., van Eijk, B., Kluit, R., Vitkovskiy, A., Benka, T., Havranek, M., Janoska, Z., Marcisovsky, M., Neue, G., Tomasek, L., Kafka, V., Vrba, V., Lopez-Morillo, E., Palomo, F. R., Muñoz, F., Vila, I., Jiménez, E. M. S., Abbaneo, D., Christiansen, J., Orfanelli, S., Casas, L. M. Jara, Conti, E., Bell, S., Prydderch, M. L., Thomas, S., Christian, D. C., Deptuch, G., Fahim, F., Hoff, J., Lipton, R., Liu, T., Zimmerman, T., Miryala, S., Garcia-Sciveres, M., Gnani, D., Krieger, A., Papadopoulou, K., Heim, T., Carney, R., Nachman, B., Renteira, C., Wallangen, V., Hoeferkamp, M., and Seidel, S., ?Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC?, in 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), 2018.

A.  Franceschin, Padovan, F., Nonis, R., and Bevilacqua, A., ?On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 657 - 661, 2018.

F.  Padovan, Quadrelli, F., Bassi, M., Tiebout, M., and Bevilacqua, A., ?A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations?, in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018.

F.  Pepe, Bevilacqua, A., and Andreani, P., ?On the Remarkable Performance of the Series-Resonance CMOS Oscillator?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 531-542, 2018.

A.  Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., ?A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE?, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.

F.  Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset?, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.

F.  Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation?, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.

F.  Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers?, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.

S.  Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., ?A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.

A.  Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., ?Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers?, Analog Integrated Circuits and Signal Processing, vol. 89, no. 2, pp. 307-315, 2016.

F.  Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., ?A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation?, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.

A.  Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., ?Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs?, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015, 2015, pp. 1-4.

F.  Padovan, Tiebout, M., Mertens, K. L. R., Bevilacqua, A., and Neviani, A., ?Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 607-615, 2015.

F.  Padovan, Tiebout, M., Dielacher, F., Bevilacqua, A., and Neviani, A., ?SiGe BiCMOS VCO with 27% tuning range for 5G communications?, in 2015 Asia-Pacific Microwave Conference (APMC), 2015, vol. 1, pp. 1-3.

F.  Padovan, Bevilacqua, A., and Neviani, A., ?A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS?, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 287-290.

A.  Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., ?A linear model of efficiency for Switched-Capacitor RF Power-Amplifiers?, in 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2014, pp. 1-4.

F.  Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., ?A K-band SiGe bipolar VCO with transformer-coupled varactor for backhaul links?, in 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF),, 2013, pp. 108-110.

F.  Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., ?A SiGe bipolar VCO for backhaul E-band communication systems?, in Proceedings of the 2012 ESSCIRC, 2012, pp. 402 -405.

A.  Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., ?Transformer-Based Dual-Mode Voltage-Controlled Oscillators?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, pp. 293 -297, 2007.

A.  Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., ?A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO?, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.

M.  PERENZONI, Gerosa, A., and Neviani, A., ?Analog CMOS Implementation of Gallager?s Interative Decoding algorithm applied to a Block Turbo Code?, in ISCAS, 2003, vol. 5, pp. 813?816.

A.  Gerosa, Bernardini, R., and Pietri, S., ?A Fully Integrated Chaotic System for the Generation of Truly Random Numbers?, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, vol. 49, pp. 993?1000, 2002.

A.  Gerosa, Bernardini, R., and Pietri, S., ?A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system?, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 87 -92.

G.  MENEGHESSO, Zanoni, E., Gerosa, A., PAVAN, P., STADLER, W., ESMARK, K., and GUGGENMOS, G., ?Test structures and testing methods for electrostatic discharge: results of PROPHECY project?, MICROELECTRONICS RELIABILITY, vol. 39, pp. 635?646, 1999.