A.  Bevilacqua and Mazzanti, A., ?On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, pp. 1777-1786, 2026.

A.  Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., ?Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs?, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.

A.  Bevilacqua and Mazzanti, A., ?Analysis of CMRR in Doubly-Tuned Transformer Baluns?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 4874-4878, 2024.

D.  Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, pp. 607-617, 2023.

A.  Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., ?A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS?, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

A.  Bettini, Cosnier, T., Magnani, A., Syshchyk, O., Borga, M., Decoutere, S., and Neviani, A., ?Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology?, in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022.

F.  Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications?, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

N.  Modolo, De Santi, C., Baratella, G., Bettini, A., Borga, M., Posthuma, N., Bakeroot, B., You, S., Decoutere, S., Bevilacqua, A., Neviani, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., ?Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices?, IEEE Transactions on Electron Devices, pp. 1-6, 2022.

F.  Chiocchetta, De Santi, C., Rampazzo, F., Mukherjee, K., Grünenpütt, J., Sommer, D., Blanck, H., Lambert, B., Gerosa, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., ?GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse?, in 2022 IEEE International Reliability Physics Symposium (IRPS), 2022.

A.  Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS?, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.

D.  Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., ?A 22?31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS?, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021.

A.  Bevilacqua and Mazzanti, A., ?Doubly-Tuned Transformer Networks: A Tutorial?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, pp. 550-555, 2021.

A.  Bilato, Issakov, V., Mazzanti, A., and Bevilacqua, A., ?A Multichannel D-Band Radar Receiver With Optimized LO Distribution?, IEEE Solid-State Circuits Letters, vol. 4, pp. 141-144, 2021.

G.  Marin, Kim, J., Seo, J. - M., and Neviani, A., ?A 13.56 MHz Reconfigurable Step-Up Switched Capacitor Converter for Wireless Power Transfer System in Implantable Medical Devices?, in 2020 IEEE Wireless Power Transfer Conference (WPTC), 2020.

D.  Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., ?A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS?, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.

S.  Marconi, Spiazzi, G., Bevilacqua, A., and Galvano, M., ?A Novel Integrated Step-Up Hybrid Converter With Wide Conversion Ratio?, IEEE Transactions on Power Electronics, vol. 35, pp. 2764-2775, 2020.

G.  Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., ?Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters?, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.

G.  Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., ?A Reconfigurable Switched Capacitor DC?DC Converter With 1.9?6.3-V Input Voltage Range and 85% Peak Efficiency in 28-nm CMOS?, IEEE Solid-State Circuits Letters, vol. 3, pp. 106-109, 2020.

M.  Ruzzarin, Meneghini, M., de Santi, C., Neviani, A., Yu, F., Strempel, K., Fatahilah, M. Fahlesa, Witzigmann, B., Wasisto, H. Suryo, Waag, A., Meneghesso, G., and Zanoni, E., ?Demonstration of UV-Induced Threshold Voltage Instabilities in Vertical GaN Nanowire Array-Based Transistors?, IEEE Transactions on Electron Devices, vol. 66, pp. 2119-2124, 2019.

G.  Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., ?Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters?, in 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019.

G.  Spiazzi, Biadene, D., Marconi, S., and Bevilacqua, A., ?Non-isolated High Step-up DC-DC Converter with Minimum Switch Voltage Stress?, IEEE Transactions on Power Electronics, vol. 34, no. 2, pp. 1470-1480, 2019.

S.  Marconi, Barbero, M. B., Fougeron, D., Godiot, S., Menouni, M., Pangaud, P., Rozanov, A., Breugnon, P., Bomben, M., Calderini, G., Crescioli, F., Le Dortz, O., Marchiori, G., Dzahini, D., Rarbi, F. E., Gaglione, R., Krüger, H., Daas, M., Dieter, Y., Hemperek, T., Hügging, F., Moustakas, K., Pohl, D., Rymaszewski, P., Standke, M., Vogt, M., Wang, T., Wermes, N., Karagounis, M., Stiller, A., Marzocca, C., Marzocca, G., De Robertis, G., Loddo, F., Licciulli, F., Andreazza, A., Liberali, V., Stabile, A., Frontini, L., Bagatin, M., Bisello, D., Gerardin, S., Mattiazzo, S., Paccagnella, A., Vogrig, D., Bonaldo, S., Bacchetta, N., Gaioni, L., De Canio, F., Manghisoni, M., Re, V., Riceputi, E., Traversi, G., Ratti, L., Vacchi, C., Androsov, K., Beccherle, R., Magazzu, G., Minuti, M., Morsani, F., Palla, F., Poulios, S., Bilei, G. M., Menichelli, M., Placidi, P., Dellacasa, G., Demaria, N., Mazza, G., Monteil, E., Pacher, L., Paternò, A., Rivetti, A., Rolo, M. D. Da Roch, Gajanana, D., Gromov, V., van Eijk, B., Kluit, R., Vitkovskiy, A., Benka, T., Havranek, M., Janoska, Z., Marcisovsky, M., Neue, G., Tomasek, L., Kafka, V., Vrba, V., Lopez-Morillo, E., Palomo, F. R., Muñoz, F., Vila, I., Jiménez, E. M. S., Abbaneo, D., Christiansen, J., Orfanelli, S., Casas, L. M. Jara, Conti, E., Bell, S., Prydderch, M. L., Thomas, S., Christian, D. C., Deptuch, G., Fahim, F., Hoff, J., Lipton, R., Liu, T., Zimmerman, T., Miryala, S., Garcia-Sciveres, M., Gnani, D., Krieger, A., Papadopoulou, K., Heim, T., Carney, R., Nachman, B., Renteira, C., Wallangen, V., Hoeferkamp, M., and Seidel, S., ?Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC?, in 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), 2018.

A.  Mazzanti and Bevilacqua, A., ?Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4157 - 4168, 2018.

G.  Spiazzi, Biadene, D., Marconi, S., and Bevilacqua, A., ?Non-isolated high step-up DC-DC converter with minimum switch voltage stress?, in 2017 IEEE Southern Power Electronics Conference (SPEC), 2017.

G.  Spiazzi, Marconi, S., and Bevilacqua, A., ?Step-Up DC-DC converters combining basic topologies with charge pump?, in 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), 2016, pp. 1-6.

M.  Bassi, Zhao, J., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., ?A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP?, IEEE Journal of Solid-State Circuits, vol. 50, pp. 1618-1628, 2015.

F.  Padovan, Tiebout, M., Mertens, K. L. R., Bevilacqua, A., and Neviani, A., ?Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 607-615, 2015.

A.  Mazzanti and Bevilacqua, A., ?On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 2334-2341, 2015.

J.  Zhao, Bassi, M., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., ?A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP?, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 179-182.

F.  Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., ?A K-band SiGe bipolar VCO with transformer-coupled varactor for backhaul links?, in 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF),, 2013, pp. 108-110.

F.  Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., ?A SiGe bipolar VCO for backhaul E-band communication systems?, in Proceedings of the 2012 ESSCIRC, 2012, pp. 402 -405.

S. D.  Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, in Digest of Technical Papers of 2008 IEEE International Solid-State Circuits Conference, 2008, pp. 124 -601.

S.  Dal Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., ?UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking?, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2844 -2852, 2008.

A.  Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., ?An Integrated Solution for Suppressing WLAN Signals in UWB Receivers?, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, pp. 1617 -1625, 2007.

A.  Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., ?A 0.35 um SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection?, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 1015 -1018.

A.  Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., Neviani, A., and Gerosa, A., ?CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code?, in Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE, 2006, pp. 1 -6.

A.  Graell i Amat, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., ?Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code?, Communications, IEEE Transactions on, vol. 54, pp. 1973 -1982, 2006.

A.  Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., SOLDA, S., Neviani, A., and Gerosa, A., ?Iterative Analog Decoder for a SCCC?, in Analog Decoding Workshop, 2006.

A.  Maniero, Bevilacqua, A., Gerosa, A., and Neviani, A., ?A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency?, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 90 -93.

D.  Vogrig, Gerosa, A., Neviani, A., Amat, A. G., Montorsi, G., and Benedetto, S., ?A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code?, Solid-State Circuits, IEEE Journal of, vol. 40, pp. 753 - 762, 2005.

D.  Vogrig, Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., and Benedetto, S., ?A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code?, in Research in Microelectronics and Electronics, 2005 PhD, 2005, vol. 1, pp. 31 - 34 vol.1.

A. G. I.  Amatt, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., ?An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code?, in Communications, 2005. ICC 2005. 2005 IEEE International Conference on, 2005, vol. 1, pp. 663 - 667 Vol. 1.

A.  Graell i Amat, Montorsi, G., Benedetto, S., Vogrig, D., Neviani, A., and Gerosa, A., ?An analog turbo decoder for the UMTS standard?, in Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on, 2004, p. 296.

A.  Gerosa, Maniero, A., and Neviani, A., ?A Fully-Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemakers?, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, vol. 51, pp. 1916?1925, 2004.

A.  Gerosa, Neviani, A., and Maniero, A., ?A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers?, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 39, pp. 1083?1093, 2004.

A.  Gerosa, Xotta, A., Neviani, A., and Mian, G. A., ?Frequency Offset Compensation in Fractionally Spaced Equalization?, IEE PROCEEDINGS. CIRCUITS, DEVICES AND SYSTEMS, vol. 150, pp. 134?140, 2003.

A.  Gerosa, Maniero, A., and Neviani, A., ?A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers?, in ESSCIRC, 2003, vol. 1, pp. 157?160.

A.  Maniero, Gerosa, A., and Neviani, A., ?Performance Optimization in Micro-Power, Low-Voltage, Log-Domain Filters in Pure CMOS Technology?, in ISCAS, 2003, vol. 1, pp. 565?568.

A.  Xotta, Vogrig, D., Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., Bruccoleri, M., and Betti, G., ?An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels?, in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, 2002, vol. 5, p. V-69 - V-72 vol.5.

A.  Gerosa, Novo, A., Mengalli, A., and Neviani, A., ?A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker?, in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001, vol. 1, pp. 296 -299 vol. 1.

A.  Gerosa, Neviani, A., Xotta, A., and Mian, G. A., ?A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization?, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 1099 -1102 vol.2.

A.  Novo, Gerosa, A., Neviani, A., Mozzi, A., and Zanoni, E., ?A CMOS 0.8 um programmable charge pump for the output stage of an implantable pacemaker?, in Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on, 2000, pp. 34/1 -34/5.

A.  Gerosa, Cortelazzo, G. M., Baschirotto, A., and Malavasi, E., ?2D video rate SC FIR filters based on analog RAMs?, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 46, pp. 1348 -1360, 1999.

A.  Gerosa and Mian, G. A., ?A low complexity EPR-IV equalizer for hard disk read channels?, in Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on, 1999, vol. 2, pp. 1069 -1072 vol.2.

A.  Novo, Gerosa, A., Neviani, A., Mozzi, A., and Zanoni, E., ?Programmable voltage multiplier for pacemaker output pulse generation?, Electronics Letters, vol. 35, pp. 560 -561, 1999.

A.  Novo, Gerosa, A., Neviani, A., Zanoni, E., and Mozzi, A., ?Programmable voltage multipliers for pacemaker output pulse generation in CMOS 0.8 um technology?, in Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European, 1999, pp. 386 - 389.

G.  MENEGHESSO, Zanoni, E., Gerosa, A., PAVAN, P., STADLER, W., ESMARK, K., and GUGGENMOS, G., ?Test structures and testing methods for electrostatic discharge: results of PROPHECY project?, MICROELECTRONICS RELIABILITY, vol. 39, pp. 635?646, 1999.

A.  Gerosa and Mian, G. A., ?An Equalizer for Hard Disk Drive Channels, with Low Sensitivity to Sampling Phase Variation?, in EUSIPCO-98, 1998, vol. 1, pp. 483?486.

G. M.  Cortelazzo, Malavasi, E., Gerosa, A., and Neviani, A., ?A New Structure for Video-Rate 2D SC FIR Filters?, in EUSIPCO-96, 1996, vol. 2, pp. 1307?1310.