L.  Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., ?A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1?s?, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

A.  Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., ?Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs?, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.

L.  Tomasin, Iesurum, A., Gobbo, A., Neviani, A., and Bevilacqua, A., ?A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies?, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 4718-4722, 2024.

F.  Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., ?A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner?, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

A.  Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., ?A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS?, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., ?A 68.6fs_rms-Total-integrated-Jitter and 1.5?s-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching?, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

S. M.  Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., ?A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 ? s-Locking-Time?, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.

A.  Bilato, Issakov, V., Mazzanti, A., and Bevilacqua, A., ?A Multichannel D-Band Radar Receiver With Optimized LO Distribution?, IEEE Solid-State Circuits Letters, vol. 4, pp. 141-144, 2021.

A.  Bilato, Issakov, V., and Bevilacqua, A., ?A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 ?m SiGe BiCMOS?, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

A.  Bilato, Issakov, V., and Bevilacqua, A., ?Considerations on 120GHz LO Signal Generation and Distribution for Highly-Integrated Multi-Channel Radar Transceivers?, in 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019.